1. Field
The following description relates to a memory control technique for controlling memory access of a plurality of load/store units.
2. Description of the Related Art
As the development of information and communication technologies have increased, so have various computer systems, such as a smart phone, a digital camera, a digital TV, and the like. Recently developed computer systems are typically provided with a high-speed processor. The high-speed processor is accompanied with a high-speed memory controller to support high-speed performance.
Generally, a memory controller receives memory access requests, for example, data read requests, data write requests, and the like. The requests may be received from various processing units, for example, a Central Processing Unit (CPU), a graphics accelerator, and the like in a computer system. The memory controller processes the memory access requests.
For example, the memory controller may receive a data load request from a CPU, read the requested data from a memory in response to the memory load request, and return the read data to the CPU. At this time, the CPU may generate a predetermined stall in order to wait to receive the requested data in consideration of predetermined load latency. During a stall, the operational state of CPU is stopped. The frequent generation of stalls results in performance deterioration of system.